This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-02-15 04:25:57 +00:00
Code
Issues
Releases
Wiki
Activity
Files
d0d7a360edb08abf4dce6e37f61eea0a6e6ef045
YosysHQ.yosys
/
frontends
/
ast
History
David Shah
09311b6581
dpi: Support for chandle type
...
Signed-off-by: David Shah <
dave@ds0.me
>
2021-01-23 22:24:31 +00:00
..
ast.cc
Return correct modname when found in cache.
2020-11-26 13:31:22 +01:00
ast.h
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
dpicall.cc
dpi: Support for chandle type
2021-01-23 22:24:31 +00:00
genrtlil.cc
genrtlil: fix mux2rtlil generated wire signedness
2020-12-22 17:49:16 -07:00
Makefile.inc
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
simplify.cc
Fix input/output attributes when resolving typedef of wire
2021-01-18 17:31:22 +01:00