Sylvain Munaut 86ce43999e Make return value of $clog2 signed ...

As per Verilog 2005 - 17.11.1.

Fixes #708

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

2018-11-24 18:49:23 +01:00

..

ast

Make return value of $clog2 signed

2018-11-24 18:49:23 +01:00

blif

Merge pull request #591 from hzeller/virtual-override

2018-08-15 14:05:38 +02:00

ilang

Add "make coverage"

2018-08-27 14:22:21 +02:00

json

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

liberty

Allow square brackets in liberty identifiers

2018-11-05 12:33:33 +01:00

verific

Set Verific flag vhdl_support_variable_slice=1

2018-11-09 21:03:23 +01:00

verilog

Add warning for SV "restrict" without "property"

2018-11-04 15:57:17 +01:00