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d1fbe738a76efbdbb04da7d8aa04d19d54d6e9cd
YosysHQ.yosys
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tests
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arch
History
Marcelina Kościelnicka
f61f2a4078
gowin: Fix LUT RAM inference, add more models.
2022-02-09 09:04:34 +01:00
..
anlogic
anlogic: support BRAM mapping
2021-12-17 20:28:22 +08:00
common
Allow initial blocks to be disabled during tests
2021-11-13 21:53:25 +01:00
ecp5
abc9: replace cell type/parameters if derived type already processed (
#2991
)
2021-09-09 10:05:55 -07:00
efinix
…
gatemate
Add gitignore for gatemate
2021-12-03 09:56:37 +01:00
gowin
gowin: Fix LUT RAM inference, add more models.
2022-02-09 09:04:34 +01:00
ice40
…
intel_alm
…
machxo2
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
nexus
…
quicklogic
…
xilinx
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
run-test.sh
…