Clifford Wolf c7afbd9d8e Fixed bug in "read_verilog -ignore_redef"

2014-08-15 01:53:22 +02:00

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ast

Fixed bug in "read_verilog -ignore_redef"

2014-08-15 01:53:22 +02:00

ilang

Added module->ports

2014-08-14 16:22:52 +02:00

liberty

More bugfixes related to new RTLIL::IdString

2014-08-02 18:14:21 +02:00

verific

Fixed building verific bindings

2014-08-12 15:21:06 +02:00

verilog

Fixed line numbers when using here-doc macros

2014-08-14 22:26:30 +02:00

vhdl2verilog

Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

2014-07-31 13:19:47 +02:00