1
0
mirror of synced 2026-02-21 15:07:30 +00:00
Files
YosysHQ.yosys/techlibs
Tony Min d41688f7d7 Revisions (#4)
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
2024-07-08 10:57:16 -04:00
..
2024-03-18 11:33:18 +13:00
2024-03-18 11:33:18 +13:00
2024-03-18 11:33:18 +13:00
2024-03-18 11:33:18 +13:00
2024-03-18 11:33:18 +13:00
2024-05-03 11:32:33 +01:00
2024-03-18 11:33:18 +13:00
2024-07-08 10:57:16 -04:00
2024-03-18 11:33:18 +13:00
2022-09-21 15:46:43 +02:00
2023-08-12 11:59:39 +10:00