Zachary Snow d738b2c127 sv: support for parameters without default values ...

- Modules with a parameter without a default value will be automatically
  deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
  just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations

2021-03-02 10:43:53 -05:00

..

.gitignore

Add "make coverage"

2018-08-27 14:22:21 +02:00

const2ast.cc

Replacing log_error for log_file_error due consistency

2020-03-31 12:01:29 -06:00

Makefile.inc

Treat all bison warnings as errors in verilog front-end

2020-07-15 11:57:31 +02:00

preproc.cc

verilog: fix handling of nested ifdef directives

2021-03-01 12:28:33 -05:00

preproc.h

Add support for SystemVerilog-style `define to Verilog frontend

2020-03-27 16:08:26 +00:00

verilog_frontend.cc

Fix indents.

2021-01-04 00:17:16 -08:00

verilog_frontend.h

frontend: cleanup to use more ID::*, more dict<> instead of map<>

2020-05-04 10:48:37 -07:00

verilog_lexer.l

sv: extended support for integer types

2021-02-28 16:31:56 -05:00

verilog_parser.y

sv: support for parameters without default values

2021-03-02 10:43:53 -05:00