Marcelina Kościelnicka d555454969 tests/bram: Do not generate write address collisions. ...

These have no defined semantics, making the tests non-deterministic.

2021-03-08 16:53:03 +01:00

..

aiger

switch argument order to work with macOS getopt

2020-09-23 12:48:26 +02:00

arch

machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.

2021-02-23 17:39:58 +01:00

asicworld

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bram

tests/bram: Do not generate write address collisions.

2021-03-08 16:53:03 +01:00

errors

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fsm

tests: fsm to use a randomly-generated seed

2020-04-24 14:31:33 -07:00

hana

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liberty

dfflibmap: Refactor to use dfflegalize internally.

2020-07-09 18:51:03 +02:00

lut

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memfile

Added 'set -e' into tests/memfile/run-test.sh

2020-02-06 10:45:40 -03:00

memories

tests: Parallelize

2020-09-21 15:07:02 +02:00

opt

opt_share: Fix X and CO signal width for shifted $alu in opt_share.

2021-01-14 14:54:08 +01:00

opt_share

tests: Parallelize

2020-09-21 15:07:02 +02:00

proc

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realmath

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rpc

rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors

2020-03-06 15:29:01 +01:00

sat

assertpmux: Fix crash on unused $pmux output.

2021-02-22 23:30:28 +01:00

select

Merge pull request #1949 from YosysHQ/eddie/select_blackbox

2020-04-22 15:35:05 -07:00

share

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simple

verilog: fix handling of nested ifdef directives

2021-03-01 12:28:33 -05:00

simple_abc9

Set aside extraneous tests in simple_abc9 test suite

2021-03-01 12:13:11 -05:00

smv

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sva

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svinterfaces

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svtypes

Add typedef input/output test

2021-01-18 17:31:22 +01:00

techmap

Add tests for some common techmap files.

2021-02-24 01:07:34 +01:00

tools

Replace opt_rmdff with opt_dff.

2020-08-07 13:21:03 +02:00

unit

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various

Add tests for $countbits

2021-02-26 12:28:58 -05:00

verilog

Merge pull request #2626 from zachjs/param-no-default

2021-03-07 05:48:03 -08:00

vloghtb

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gen-tests-makefile.sh

tests: Parallelize

2020-09-21 15:07:02 +02:00