This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-05-05 15:45:07 +00:00
Code
Issues
Releases
Wiki
Activity
Files
d6600fb1d508fe7526b4157b8e5e66baaff367ae
YosysHQ.yosys
/
backends
/
verilog
History
Catherine
9cbfad2691
write_verilog: don't emit code with dangling else related to wrong condition.
2024-01-24 16:32:25 +00:00
..
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
verilog_backend.cc
write_verilog: don't emit code with dangling else related to wrong condition.
2024-01-24 16:32:25 +00:00