Clifford Wolf f6629b9c29 Optimize memory address port width in wreduce and memory_collect, not verilog front-end

2016-08-19 18:38:25 +02:00

..

ast.cc

Added "read_verilog -dump_rtlil"

2016-07-27 15:40:17 +02:00

ast.h

Added "read_verilog -dump_rtlil"

2016-07-27 15:40:17 +02:00

dpicall.cc

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

genrtlil.cc

Optimize memory address port width in wreduce and memory_collect, not verilog front-end

2016-08-19 18:38:25 +02:00

Makefile.inc

Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)

2014-08-21 12:43:51 +02:00

simplify.cc

Optimize memory address port width in wreduce and memory_collect, not verilog front-end

2016-08-19 18:38:25 +02:00