gatecat 48efc9b75c gatemate: Add test for LUT tree mapping ...

Signed-off-by: gatecat <gatecat@ds0.me>

2022-06-27 10:09:48 +01:00

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aiger

switch argument order to work with macOS getopt

2020-09-23 12:48:26 +02:00

arch

gatemate: Add test for LUT tree mapping

2022-06-27 10:09:48 +01:00

asicworld

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bind

Add support for parsing the SystemVerilog 'bind' construct

2021-07-16 09:31:39 -04:00

blif

Adding expected error message.

2022-06-22 00:34:49 +01:00

bram

Fix the tests we just broke

2021-12-10 00:22:37 +01:00

errors

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fsm

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hana

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liberty

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lut

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memfile

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memlib

Add memory_libmap tests.

2022-05-18 17:32:56 +02:00

memories

Fix the tests we just broke

2021-12-10 00:22:37 +01:00

opt

Add memory_bmux2rom pass.

2022-05-18 22:48:55 +02:00

opt_share

tests: Parallelize

2020-09-21 15:07:02 +02:00

proc

proc_rom: Add special handling of const-0 address bits.

2022-05-18 17:32:30 +02:00

realmath

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rpc

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sat

Proper example code

2022-03-14 15:39:11 +01:00

select

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share

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sim

test dlatchsr and adlatch

2022-02-16 13:58:51 +01:00

simple

Fix valgrind tests when using verific

2022-03-30 17:25:53 +02:00

simple_abc9

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

smv

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sva

verific: Use new value change logic also for $stable of wide signals.

2022-05-11 13:05:27 +02:00

svinterfaces

Add a test for interfaces on modules loaded on-demand

2021-07-14 22:54:50 -04:00

svtypes

sv: improve support for wire and var with user-defined types

2021-08-12 22:41:41 -06:00

techmap

opt_mem: Remove constant-value bit lanes.

2022-05-07 23:13:16 +02:00

tools

Fixes in vcdcd.pl for newer Perl versions

2021-10-19 10:56:43 +02:00

unit

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various

smt2: emit smtlib2_comb_expr outputs after all inputs

2022-06-07 19:06:45 +02:00

verilog

verilog: fix width/sign detection for functions

2022-05-30 16:45:39 -04:00

vloghtb

Use HTTPS for website links, gatecat email

2021-06-09 12:16:56 +02:00

gen-tests-makefile.sh

tests: Parallelize

2020-09-21 15:07:02 +02:00