whitequark 6f67dd8df5

Merge pull request #1683 from whitequark/write_verilog-memattrs ...

write_verilog: dump $mem cell attributes

2020-02-07 02:54:04 +00:00

..

aiger

Merge branch 'eddie/abc9_refactor' into eddie/abc9_required

2020-01-27 12:29:28 -08:00

blif

RTLIL::S{0,1} -> State::S{0,1}

2019-08-07 11:12:38 -07:00

btor

Use cell name for btor bad state props when it is a public name

2019-11-14 11:57:38 +01:00

edif

edif: more resilience to mismatched port connection sizes.

2020-02-06 18:45:03 +01:00

firrtl

Merge pull request #1258 from YosysHQ/eddie/cleanup

2019-08-10 09:52:14 +02:00

ilang

RTLIL::S{0,1} -> State::S{0,1}

2019-08-07 11:12:38 -07:00

intersynth

substr() -> compare()

2019-08-07 12:20:08 -07:00

json

json: remove the 32-bit parameter special case

2020-02-01 16:16:26 +01:00

protobuf

Add aiger and protobuf backends binary support

2019-09-28 09:51:48 +02:00

simplec

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

2019-08-06 04:47:55 +02:00

smt2

Improve yosys-smtbmc "solver not found" handling

2020-01-27 17:48:56 +01:00

smv

substr() -> compare()

2019-08-07 12:20:08 -07:00

spice

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

table

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

verilog

write_verilog: dump $mem cell attributes.

2020-02-06 16:22:42 +00:00