Clifford Wolf 96e753041d fixed freduce for Minisat::SimpSolver: use frozen_literal()

2014-03-03 02:14:27 +01:00

..

abc

Added abc -keepff option

2014-02-14 11:28:42 +01:00

cmds

Added "design -push" and "design -pop"

2014-02-20 23:28:59 +01:00

fsm

Fixes in fsm detect/extract for better detection of non-fsm circuits

2013-12-06 12:53:20 +01:00

hierarchy

Implemented read_verilog -defer

2014-02-13 13:59:13 +01:00

memory

Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect

2014-02-08 19:13:19 +01:00

opt

Fixed const folding of $bu0 cells

2014-02-27 04:09:32 +01:00

proc

Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst

2014-02-21 23:34:45 +01:00

sat

fixed freduce for Minisat::SimpSolver: use frozen_literal()

2014-03-03 02:14:27 +01:00

techmap

Added _TECHMAP_REPLACE_ feature to techmap

2014-02-20 23:42:07 +01:00