David Lanzendörfer d1b767ea8b Adding missing to Gowin tech files ...

Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip
design for my Sipeed Tang FPGA fails.

2024-08-18 19:38:31 +01:00

..

arith_map.v

gowin: Fix X output of $alu techmap

2023-05-01 17:56:41 +02:00

brams_map.v

gowin: Fix SDP write enable port.

2024-01-30 17:06:59 +10:00

brams.txt

gowin: Change BYTE ENABLE handling.

2024-01-27 17:19:49 +10:00

cells_map.v

iopadmap: Add native support for negative-polarity output enable.

2021-11-09 15:40:16 +01:00

cells_sim.v

Adding missing to Gowin tech files

2024-08-18 19:38:31 +01:00

cells_xtra.py

Gowin. Add an energy saving primitive

2024-07-06 18:58:21 +10:00

cells_xtra.v

Merge pull request #4479 from yrabbit/z1-power

2024-07-18 11:56:00 +02:00

lutrams_map.v

gowin: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

lutrams.txt

gowin: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

Makefile.inc

gowin: Add all the primitives.

2023-04-22 17:10:53 +10:00

synth_gowin.cc

Fix some synth_* help messages

2024-03-18 11:33:18 +13:00