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da360771a193707b59eac9b95b3bfe1652a057aa
YosysHQ.yosys
/
techlibs
/
xilinx
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Clifford Wolf
b64b38eea2
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
..
example_mojo_counter
…
example_sim_counter
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example_zed_counter
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cells.v
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Makefile.inc
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synth_xilinx.cc
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