YosysHQ.yosys/frontends at db98a18edb02a5c3a0c3f26efec0e01f8232790a - YosysHQ.yosys - Berget Git Service

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Clifford Wolf db98a18edb Enabled AST/Verilog front-end optimizations per default

2013-06-10 13:19:04 +02:00

..

Enabled AST/Verilog front-end optimizations per default

2013-06-10 13:19:04 +02:00

Fixed memory leak in ilang frontend

2013-05-23 12:55:59 +02:00

Enabled AST/Verilog front-end optimizations per default

2013-06-10 13:19:04 +02:00