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YosysHQ.yosys/kernel
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Marcelina Kościelnicka dc07ae9677 techmap: Add _TECHMAP_CELLNAME_ special parameter. 
This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
2020-07-21 15:00:54 +02:00
..
bitpattern.h
Removed unnecessary cast.
2015-09-01 12:40:36 +02:00
calc.cc
Add flooring division operator
2020-05-28 22:59:04 +02:00
cellaigs.cc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
cellaigs.h
…
celledges.cc
Add flooring division operator
2020-05-28 22:59:04 +02:00
celledges.h
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
celltypes.h
celltypes: Fix EN port name for some FF types.
2020-07-20 23:04:10 +02:00
consteval.h
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
constids.inc
techmap: Add _TECHMAP_CELLNAME_ special parameter.
2020-07-21 15:00:54 +02:00
cost.h
Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)
2019-08-11 11:39:46 +02:00
driver.cc
Add WASI platform support.
2020-04-30 18:56:25 +00:00
hashlib.h
dict: Remove guard for past-the-end iterators that might mask problems in static analysis.
2020-06-19 21:04:29 +00:00
log.cc
Use C++11 [[noreturn]] attribute.
2020-06-19 01:06:48 +00:00
log.h
Merge pull request #2168 from whitequark/assert-unused-exprs
2020-06-25 18:21:51 +02:00
macc.h
Use (and ignore) the expression provided to log_assert in NDEBUG builds.
2020-06-19 15:48:58 +00:00
modtools.h
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
register.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
register.h
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
rtlil.cc
Add add* functions for the new FF types
2020-06-23 15:40:02 +02:00
rtlil.h
Add add* functions for the new FF types
2020-06-23 15:40:02 +02:00
satgen.cc
satgen: Move importCell out of the header.
2020-07-19 00:17:02 +02:00
satgen.h
satgen: Move importCell out of the header.
2020-07-19 00:17:02 +02:00
sigtools.h
kernel: const Wire* overload -> Wire* !!!
2020-03-26 16:21:30 -07:00
timinginfo.h
timinginfo: ignore $specify2 cells if EN is false
2020-05-14 10:33:56 -07:00
utils.h
…
yosys.cc
verilog_backend: add -sv option, make -o <filename>.sv work.
2020-07-16 10:44:08 +00:00
yosys.h
Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).
2020-06-19 15:48:58 +00:00