Eddie Hung 3fb604c75d Revert "Add test that is expecting to fail" ...

This reverts commit c28d4b8047.

2019-10-08 12:41:26 -07:00

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.gitignore

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asserts_seq.v

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asserts_seq.ys

Added read_verilog -sv options, added support for bit, logic,

2014-06-12 11:54:20 +02:00

asserts.v

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asserts.ys

Added read_verilog -sv options, added support for bit, logic,

2014-06-12 11:54:20 +02:00

counters-repeat.v

support repeat loops with constant repeat counts outside of constant functions

2019-04-09 12:28:32 -04:00

counters-repeat.ys

support repeat loops with constant repeat counts outside of constant functions

2019-04-09 12:28:32 -04:00

counters.v

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counters.ys

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expose_dff.v

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expose_dff.ys

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initval.v

Wire with init on FF part, 1'bx on non-FF part

2019-08-24 15:05:44 -07:00

initval.ys

Revert "Add test that is expecting to fail"

2019-10-08 12:41:26 -07:00

run-test.sh

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share.v

Added yet another resource sharing test case

2014-07-20 21:15:01 +02:00

share.ys

Added yet another resource sharing test case

2014-07-20 21:15:01 +02:00

sizebits.sv

Allow $size and $bits in verilog mode, actually check test case

2017-09-29 11:56:43 +02:00

sizebits.ys

Allow $size and $bits in verilog mode, actually check test case

2017-09-29 11:56:43 +02:00

splice.v

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splice.ys

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