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YosysHQ.yosys/passes
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Clifford Wolf 10e57f3880 Fix $dlatch handling in async2sync 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-30 14:58:23 +02:00
..
cmds
Improve "portlist" command
2019-09-25 09:20:38 +02:00
equiv
Add equiv_opt -multiclock
2019-09-11 13:55:59 +01:00
fsm
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
hierarchy
Adopt @cliffordwolf's suggestion
2019-09-03 12:18:50 -07:00
memory
stoi -> atoi
2019-08-07 11:09:17 -07:00
opt
Revert "SigSet<Cell*> to use stable compare class"
2019-09-13 09:49:15 -07:00
pmgen
Ooops AREG and BREG to default to -1
2019-09-27 11:57:53 -07:00
proc
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
sat
Fix $dlatch handling in async2sync
2019-09-30 14:58:23 +02:00
techmap
Merge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 11:26:22 -07:00
tests
Document (* gentb_skip *) attr for test_autotb
2019-09-18 12:41:35 -07:00