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YosysHQ.yosys
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Eddie Hung
a181ff66d3
Add abc9_init wire, attach to abc9_flop cell
2019-12-03 18:47:09 -08:00
..
cmds
Add "autoname" pass and use it in "synth_ice40"
2019-11-13 13:41:16 +01:00
equiv
…
fsm
…
hierarchy
Use pool instead of std::set for determinism
2019-12-01 23:26:17 -08:00
memory
Merge pull request
#1501
from YosysHQ/dave/mem_copy_attr
2019-11-27 11:25:23 +01:00
opt
opt_share: Fix handling of fine cells.
2019-11-27 08:01:07 +01:00
pmgen
Check for either sign or zero extension for postAdd packing
2019-11-26 22:51:00 -08:00
proc
proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
2019-11-21 20:46:41 +00:00
sat
…
techmap
Add abc9_init wire, attach to abc9_flop cell
2019-12-03 18:47:09 -08:00
tests
…
