1
0
mirror of synced 2026-01-25 11:56:22 +00:00
Zachary Snow 0d8e5d965f Sign extend port connections where necessary
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
2020-12-18 20:33:14 -07:00
..
2020-11-20 08:45:55 +00:00
2020-09-21 15:07:02 +02:00
2020-10-08 18:05:51 +02:00
2020-09-21 15:07:02 +02:00
2020-08-07 13:21:03 +02:00
2020-09-21 15:07:02 +02:00