These updates should not be necessary. In fact, if they were necessary, this code would be buggy, because the results would depend on the order in which wires are traversed: If wire A is retained, which causes an update to `used_signals`, which then causes wire B to be retained when it otherwise wouldn't be, then we would get different results depending on whether A is visited before B. These updates will also make it difficult to process these wires in parallel.
11 lines
133 B
Plaintext
11 lines
133 B
Plaintext
read_rtlil << EOT
|
|
module \test
|
|
wire \wire_a
|
|
wire \wire_f
|
|
connect \wire_f \wire_a
|
|
end
|
|
EOT
|
|
|
|
opt_clean
|
|
select -assert-count 0 */*
|