1
0
mirror of synced 2026-04-14 09:19:24 +00:00
Files
YosysHQ.yosys/frontends/ast
Clifford Wolf 3d27c1cc80 Merge pull request #513 from udif/pr_reg_wire_error
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00
..
2015-07-02 11:14:30 +02:00