Jim Lawson 3b8c917025 Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences. ...

Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.

2019-07-31 09:27:38 -07:00

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.gitignore

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aes_kexp128.v

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always01.v

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always02.v

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always03.v

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arraycells.v

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arrays01.v

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arrays02.sv

Add proper test for SV-style arrays

2019-06-20 12:06:07 +02:00

attrib01_module.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib02_port_decl.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib03_parameter.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib04_net_var.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib05_port_conn.v.DISABLED

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib06_operator_suffix.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib07_func_call.v.DISABLED

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib08_mod_inst.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib09_case.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

carryadd.v

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constmuldivmod.v

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constpower.v

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defvalue.sv

Add defvalue test, minor autotest fixes for .sv files

2019-06-19 12:12:08 +02:00

dff_different_styles.v

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dff_init.v

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fiedler-cooley.v

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forgen01.v

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forgen02.v

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forloops.v

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fsm.v

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generate.v

Add test

2019-06-20 16:07:22 -07:00

graphtest.v

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hierarchy.v

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hierdefparam.v

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i2c_master_tests.v

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implicit_ports.v

Rename implicit_ports.sv test to implicit_ports.v

2019-06-07 13:12:25 +02:00

localparam_attr.v

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loops.v

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macros.v

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mem2reg.v

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mem_arst.v

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memory.v

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multiplier.v

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muxtree.v

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omsp_dbg_uart.v

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operators.v

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param_attr.v

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paramods.v

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partsel.v

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peepopt.v

Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047

2019-05-28 17:17:56 +02:00

process.v

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realexpr.v

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repwhile.v

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retime.v

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rotate.v

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run-test.sh

SystemVerilog support for implicit named port connections

2019-06-06 18:07:49 +02:00

scopes.v

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signedexpr.v

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sincos.v

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specify.v

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subbytes.v

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task_func.v

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undef_eqx_nex.v

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usb_phy_tests.v

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values.v

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vloghammer.v

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wandwor.v

Add actual wandwor test that is part of "make test"

2019-05-28 16:42:50 +02:00

wreduce.v

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xfirrtl

Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.

2019-07-31 09:27:38 -07:00