Clifford Wolf a926a6afc2 Remember global declarations and defines accross read_verilog calls

2016-11-15 12:42:43 +01:00

..

bitpattern.h

Removed unnecessary cast.

2015-09-01 12:40:36 +02:00

calc.cc

Import more std:: stuff into Yosys namespace

2015-10-25 19:30:49 +01:00

cellaigs.cc

Import more std:: stuff into Yosys namespace

2015-10-25 19:30:49 +01:00

cellaigs.h

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

celledges.cc

Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()

2016-07-25 16:39:25 +02:00

celledges.h

Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()

2016-07-25 16:39:25 +02:00

celltypes.h

Added $anyseq cell type

2016-10-14 15:24:03 +02:00

consteval.h

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

cost.h

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

driver.cc

Some minor build fixes for Visual C

2016-10-14 18:36:02 +02:00

hashlib.h

Added missing "#define HASHLIB_H"

2016-05-14 11:43:20 +02:00

log.cc

Some minor build fixes for Visual C

2016-10-14 18:36:02 +02:00

log.h

Added log_const() API

2016-08-09 19:56:10 +02:00

macc.h

Import more std:: stuff into Yosys namespace

2015-10-25 19:30:49 +01:00

modtools.h

Fixed some visual studio warnings

2016-02-13 17:31:24 +01:00

register.cc

Added glob support to all front-ends

2016-08-22 15:05:57 +02:00

register.h

Added ScriptPass helper class for script-like passes

2016-03-31 11:16:34 +02:00

rtlil.cc

Remember global declarations and defines accross read_verilog calls

2016-11-15 12:42:43 +01:00

rtlil.h

Remember global declarations and defines accross read_verilog calls

2016-11-15 12:42:43 +01:00

satgen.h

Added $anyseq cell type

2016-10-14 15:24:03 +02:00

sigtools.h

SigMap performance improvement

2016-02-01 10:10:20 +01:00

utils.h

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

yosys.cc

Added glob support to all front-ends

2016-08-22 15:05:57 +02:00

yosys.h

define PATH_MAX if not defined by limits.h

2016-10-11 12:12:09 +02:00