This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-04-19 18:53:16 +00:00
Code
Issues
Releases
Wiki
Activity
Files
e0a6742935b423991668e0fe901d676782db5648
YosysHQ.yosys
/
techlibs
/
efinix
History
Miodrag Milanovic
8badd4d812
better handling of lut and begin/end add
2019-09-18 17:45:07 +02:00
..
arith_map.v
Fix formating
2019-08-11 17:05:24 +02:00
bram.txt
…
brams_map.v
one bit enable signal
2019-08-11 13:59:39 +02:00
cells_map.v
fix mixing signals on FF mapping
2019-08-11 11:40:15 +02:00
cells_sim.v
better handling of lut and begin/end add
2019-09-18 17:45:07 +02:00
efinix_fixcarry.cc
Adding new pass to fix carry chain
2019-08-11 10:17:49 +02:00
efinix_gbuf.cc
clock for ram trough gbuf
2019-08-04 12:17:55 +02:00
Makefile.inc
Fix missing newline at end of file
2019-08-22 18:06:36 +02:00
synth_efinix.cc
Replaced custom step with setundef
2019-08-11 11:01:46 +02:00