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YosysHQ.yosys/docs/resources/PRESENTATION_ExAdv/sym_mul_cells.v
2023-08-07 12:58:40 +12:00

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Verilog

module MYMUL(A, B, Y);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output [WIDTH-1:0] Y;
assign Y = A * B;
endmodule