Clifford Wolf 42348cddd9 Merge pull request #63 from wluker/verilog-backend-mem ...

Fixed bug in $mem cell verilog code generation.

2015-05-11 21:38:06 +02:00

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blif

Added write_blif -attr

2015-03-02 23:47:45 +01:00

btor

Removed "techmap -share_map" (use "-map +/filename" instead)

2015-04-08 12:13:53 +02:00

edif

Added EDIF backend support for multi-bit cell ports

2015-02-01 15:43:35 +01:00

ilang

Shorter "dump" options

2015-01-31 23:52:36 +01:00

intersynth

namespace Yosys

2014-09-27 16:17:53 +02:00

json

Added "port_directions" to write_json output

2015-04-06 01:49:58 +02:00

smt2

Added $assume support to write_smt2

2015-02-26 19:02:55 +01:00

spice

Renamed extend() to extend_xx(), changed most users to extend_u0()

2014-12-24 09:51:17 +01:00

verilog

Merge pull request #63 from wluker/verilog-backend-mem

2015-05-11 21:38:06 +02:00