Eddie Hung 4ca847a217 Merge remote-tracking branch 'origin/xaig' into xc7mux

2019-06-18 11:49:54 -07:00

..

tests

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.gitignore

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abc_xc7.box

As per @daveshah1 remove async DFF timing from xilinx

2019-06-14 12:43:20 -07:00

abc_xc7.lut

Simplify comment

2019-06-17 19:14:41 -07:00

arith_map.v

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brams_bb.v

Remove WIP ABC9 flop support

2019-06-14 10:37:52 -07:00

brams_init.py

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brams_map.v

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brams.txt

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cells_map.v

Revert "Remove wide mux inference"

2019-06-14 12:50:24 -07:00

cells_sim.v

Remove WIP ABC9 flop support

2019-06-14 10:37:52 -07:00

cells_xtra.sh

Typo

2019-05-28 09:36:01 -07:00

cells_xtra.v

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drams_map.v

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drams.txt

Add "min bits" and "min wports" to xilinx dram rules

2019-05-23 11:32:28 -07:00

ff_map.v

Cleanup

2019-06-05 12:28:46 -07:00

lut_map.v

Really permute Xilinx LUT mappings as default LUT6.I5:A6

2019-06-18 11:48:48 -07:00

Makefile.inc

Revert "Remove wide mux inference"

2019-06-14 12:50:24 -07:00

mux_map.v

Revert "Remove wide mux inference"

2019-06-14 12:50:24 -07:00

synth_xilinx.cc

Try -W 300

2019-06-17 10:29:06 -07:00