github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-21 02:18:17 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/techlibs/xilinx
History
Eddie Hung 5b5756b91e Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00
..
tests
Add pattern detection support for DSP48E1 model, check against vendor
2019-09-18 10:45:04 -07:00
.gitignore
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
abc_map.v
Add techmap_autopurge to outputs in abc_map.v too
2019-09-23 21:56:28 -07:00
abc_model.v
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
2019-09-25 10:33:16 -07:00
abc_unmap.v
Add (* techmap_autopurge *) to abc_unmap.v too
2019-09-23 22:02:22 -07:00
abc_xc7_nowide.lut
Add _nowide variants of LUT libraries in -nowidelut flows
2019-06-26 10:23:29 -07:00
abc_xc7.box
Merge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 11:26:22 -07:00
abc_xc7.lut
Simplify comment
2019-06-17 19:14:41 -07:00
arith_map.v
Instead of MUXCY/XORCY use CARRY4 (with timing)
2019-05-21 16:19:45 -07:00
brams_init.py
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
cells_map.v
Use abc_{map,unmap,model}.v
2019-08-20 12:39:11 -07:00
cells_sim.v
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00
cells_xtra.py
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00
dsp_map.v
D is 25 bits not 24 bits wide
2019-09-19 15:55:49 -07:00
lut_map.v
Really permute Xilinx LUT mappings as default LUT6.I5:A6
2019-06-18 11:48:48 -07:00
lutrams_map.v
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
lutrams.txt
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
Makefile.inc
Revert "Add a xilinx_finalise pass"
2019-09-23 19:52:55 -07:00
mux_map.v
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
synth_xilinx.cc
Merge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 11:26:22 -07:00
xc6s_brams_bb.v
move attributes to wires
2019-08-13 19:36:59 +00:00
xc6s_brams_map.v
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
xc6s_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc6s_cells_xtra.v
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00
xc6s_ff_map.v
synth_xilinx: Support latches, remove used-up FF init values.
2019-09-30 12:52:43 +02:00
xc6v_cells_xtra.v
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00
xc7_brams_bb.v
Use extractinv for synth_xilinx -ise
2019-09-19 04:02:48 +02:00
xc7_brams_map.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_cells_xtra.v
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00
xc7_ff_map.v
synth_xilinx: Support latches, remove used-up FF init values.
2019-09-30 12:52:43 +02:00
xcu_cells_xtra.v
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00