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YosysHQ.yosys/techlibs/xilinx
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David Shah e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 10:52:04 +01:00
..
tests
DSP48E1 sim model: seq test working
2019-08-08 10:52:04 +01:00
.gitignore
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
abc_xc7_nowide.lut
Add _nowide variants of LUT libraries in -nowidelut flows
2019-06-26 10:23:29 -07:00
abc_xc7.box
Fix $__XILINX_MUXF78 box timing
2019-07-01 14:04:06 -07:00
abc_xc7.lut
Simplify comment
2019-06-17 19:14:41 -07:00
arith_map.v
Instead of MUXCY/XORCY use CARRY4 (with timing)
2019-05-21 16:19:45 -07:00
brams_init.py
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
cells_map.v
xilinx: Fix missing cell name underscore in cells_map.v
2019-07-25 08:19:07 +01:00
cells_sim.v
DSP48E1 sim model: seq test working
2019-08-08 10:52:04 +01:00
cells_xtra.sh
Merge remote-tracking branch 'origin/master' into xaig
2019-06-25 09:33:11 -07:00
cells_xtra.v
Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim
2019-07-15 11:13:22 -07:00
drams_map.v
Add RAM32X1D support
2019-06-24 16:16:50 -07:00
drams.txt
Add RAM32X1D support
2019-06-24 16:16:50 -07:00
dsp_map.v
Add params
2019-07-18 21:02:49 -07:00
ff_map.v
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
2019-07-11 21:13:12 +02:00
lut_map.v
Really permute Xilinx LUT mappings as default LUT6.I5:A6
2019-06-18 11:48:48 -07:00
Makefile.inc
Oops forgot these files
2019-07-15 15:03:15 -07:00
mux_map.v
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
synth_xilinx.cc
Change $__softmul back to $mul
2019-08-01 12:45:14 -07:00
xc6s_brams_bb.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc6s_brams_map.v
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
xc6s_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_brams_bb.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_brams_map.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00