Clifford Wolf a923a63a89 Ignore celldefine directive in verilog front-end

2015-03-25 19:46:12 +01:00

..

.gitignore

Updated .gitignore file for ilang and verilog frontends

2014-10-15 01:14:38 +02:00

const2ast.cc

Fixed two minor bugs in constant parsing

2014-11-24 14:39:24 +01:00

Makefile.inc

Enable bison to be customized

2015-01-08 09:56:20 -02:00

preproc.cc

Fixed handling of "//" in filenames in verilog pre-processor

2015-02-14 08:41:03 +01:00

verilog_frontend.cc

Added non-std verilog assume() statement

2015-02-26 18:47:39 +01:00

verilog_frontend.h

Added non-std verilog assume() statement

2015-02-26 18:47:39 +01:00

verilog_lexer.l

Ignore celldefine directive in verilog front-end

2015-03-25 19:46:12 +01:00

verilog_parser.y

Added non-std verilog assume() statement

2015-02-26 18:47:39 +01:00