1
0
mirror of synced 2026-02-19 22:25:06 +00:00
Files
YosysHQ.yosys/kernel
Martin Povišer e82e5f8b13 rtlil: Adjust internal check for $mem_v2 cells
There's a mismatch between what `kernel/mem.cc` emits for memories
with no read ports and what the internal RTLIL check expects.

The point of dispute it whether some of the parameters relating to read
ports have a zero-width value in this case. The `mem.cc` code says no,
the internal checker says yes.

Surveying the other `$mem_v2` parameters, and internal cell parameters
in general, I am inclined to side with the `mem.cc` code.

This breaks RTLIL compatibility but for an obscure edge case.
2024-11-08 15:18:43 +01:00
..
2024-09-17 10:46:20 +02:00
2024-10-15 07:23:45 +13:00
2024-09-17 10:46:20 +02:00
2024-09-05 11:17:12 +02:00
2024-08-16 04:30:31 +12:00
2024-09-24 17:47:46 +02:00
2024-10-18 11:31:20 +02:00
2024-02-06 18:01:26 +01:00
2024-02-06 18:01:26 +01:00
2024-07-18 16:02:11 +02:00
2023-01-11 18:07:16 +01:00