Clifford Wolf e9506bb2da Supercell creation for $div/$mod worked all along, fixed test benches

2014-07-20 18:54:06 +02:00

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asicworld

Added note to "make test": use git checkout of iverilog

2014-07-16 10:03:07 +02:00

hana

Added note to "make test": use git checkout of iverilog

2014-07-16 10:03:07 +02:00

memories

Added SAT-based write-port sharing to memory_share

2014-07-19 15:33:55 +02:00

realmath

Added note to "make test": use git checkout of iverilog

2014-07-16 10:03:07 +02:00

sat

now ignore init attributes on non-register wires in sat command

2014-07-05 11:18:38 +02:00

share

Supercell creation for $div/$mod worked all along, fixed test benches

2014-07-20 18:54:06 +02:00

simple

Implemented dynamic bit-/part-select for memory writes

2014-07-17 16:49:23 +02:00

techmap

Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface

2014-07-16 14:08:51 +02:00

tools

Also simulate unmapped memories in "make test"

2014-07-17 16:53:52 +02:00

vloghtb

Supercell creation for $div/$mod worked all along, fixed test benches

2014-07-20 18:54:06 +02:00