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YosysHQ.yosys/frontends
whitequark e97e33d00d kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00
..
2019-08-07 11:09:17 -07:00
2019-10-04 16:29:46 +02:00