YosysHQ.yosys/tests/liberty/semicolmissing.lib.verilogsim.ok

module fulladder (A, B, CI, CO, Y);
  input A;
  input B;
  input CI;
  output CO;
  assign CO = (((A&B)|(B&CI))|(CI&A)); // "(((A * B)+(B * CI))+(CI * A))"
  output Y;
  assign Y = ((A^B)^CI); // "((A^B)^CI)"
endmodule