Robert O'Callahan 8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.

2025-07-22 10:38:38 +00:00

..

check_map_lut6.ys

Forgot to commit

2019-07-16 12:44:26 -07:00

check_map.ys

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

map_and.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

map_cmp.v

Add tests for cmp2lut on LUT6

2019-07-16 12:11:59 -07:00

map_mux.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

map_not.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

map_or.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

map_xor.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

run-test.sh

tests: use /usr/bin/env for bash.

2023-08-12 11:59:39 +10:00