YosysHQ.yosys/tests/sat/sizebits.ys at eab3272cdeed697bdb9664c2d8a133d336addb7c - YosysHQ.yosys - Berget Git Service

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Clifford Wolf dbfd8460a9 Allow $size and $bits in verilog mode, actually check test case

2017-09-29 11:56:43 +02:00

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	`read_verilog -sv sizebits.sv`
	`prep; sat -verify -prove-asserts`