Clifford Wolf 0bc95f1e04 Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

..

.gitignore

Updated .gitignore file for ilang and verilog frontends

2014-10-15 01:14:38 +02:00

const2ast.cc

Fixed segfault on invalid verilog constant 1'b_

2015-09-22 08:13:09 +02:00

Makefile.inc

Adjust makefiles to work with out-of-tree builds

2015-08-12 15:04:44 +02:00

preproc.cc

SystemVerilog also has assume(), added implicit -D FORMAL

2015-10-13 14:21:20 +02:00

verilog_frontend.cc

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

verilog_frontend.h

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

verilog_lexer.l

SystemVerilog also has assume(), added implicit -D FORMAL

2015-10-13 14:21:20 +02:00

verilog_parser.y

Fixed handling of parameters and const functions in casex/casez pattern

2016-04-21 15:31:54 +02:00