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YosysHQ.yosys/techlibs/analogdevices/lutrams.txt
2026-02-19 10:59:59 +00:00

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# Single-port RAMs.
ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
option "ABITS" 5 {
cost 1;
abits 5;
}
option "ABITS" 6 {
cost 2;
abits 6;
}
width 1;
init no_undef;
prune_rom;
port arsw "RW" {
clock anyedge;
}
}
# Dual-port RAMs.
ram distributed $__ANALOGDEVICES_LUTRAM_DP_ {
option "ABITS" 5 {
cost 2;
abits 5;
}
option "ABITS" 6 {
cost 4;
abits 6;
}
width 1;
init no_undef;
prune_rom;
port arsw "RW" {
clock posedge;
}
port ar "R" {
}
}