1
0
mirror of synced 2026-02-21 15:07:30 +00:00
Files
YosysHQ.yosys/tests/arch/analogdevices/bug3670.ys
2026-02-19 10:59:59 +00:00

4 lines
83 B
Plaintext

read_verilog bug3670.v
read_verilog -lib -specify +/analogdevices/cells_sim.v
abc9