46 lines
1.6 KiB
Plaintext
46 lines
1.6 KiB
Plaintext
read_verilog ../common/dffs.v
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design -save read
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hierarchy -top dff
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proc
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equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:FFRE
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select -assert-none t:BUFG t:FFRE %% t:* %D
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design -load read
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hierarchy -top dffe
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proc
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equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:FFRE
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select -assert-none t:BUFG t:FFRE %% t:* %D
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design -load read
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hierarchy -top dff
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proc
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equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:FFRE
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select -assert-none t:BUFG t:FFRE %% t:* %D
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design -load read
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hierarchy -top dffe
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proc
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equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:FFRE
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select -assert-none t:BUFG t:FFRE %% t:* %D
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