12 lines
448 B
Plaintext
12 lines
448 B
Plaintext
read_verilog ../common/counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -multiclock -map +/nexus/cells_sim.v synth_nexus # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 5 t:CCU2
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select -assert-count 8 t:FD1P3DX
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select -assert-none t:CCU2 t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D
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