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YosysHQ.yosys/tests/sdc/alu_sub.ys
2025-11-19 15:26:02 +01:00

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read_verilog alu_sub.v
proc
hierarchy -auto-top
select -assert-mod-count 1 adder
select -assert-mod-count 1 wrapper
select -assert-mod-count 1 alu
sdc -keep_hierarchy alu_sub.sdc
flatten
select -assert-mod-count 0 adder
select -assert-mod-count 1 wrapper
select -assert-mod-count 1 alu