Jannis Harder aa7e7df19f simlib: Simplify recently changed $mux model ...

The use of a procedural continuous assignment introduced in #3526 was
unintended and is completely unnecessary for the actual change of that
PR.

2022-10-28 19:48:00 +02:00

..

.gitignore

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abc9_map.v

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abc9_model.v

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abc9_unmap.v

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adff2dff.v

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cellhelp.py

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cells.lib

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cmp2lcu.v

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cmp2lut.v

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dff2ff.v

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gate2lut.v

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gen_fine_ffs.py

Add $aldff and $aldffe: flip-flops with async load.

2021-10-02 18:12:52 +02:00

Makefile.inc

Add smtmap.v describing the smt2 backend's behavior for undef bits

2022-10-20 15:48:18 +02:00

mul2dsp.v

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pmux2mux.v

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prep.cc

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simcells.v

Add $aldff and $aldffe: flip-flops with async load.

2021-10-02 18:12:52 +02:00

simlib.v

simlib: Simplify recently changed $mux model

2022-10-28 19:48:00 +02:00

smtmap.v

Add smtmap.v describing the smt2 backend's behavior for undef bits

2022-10-20 15:48:18 +02:00

synth.cc

Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.

2022-06-02 23:16:12 +02:00

techmap.v

Add $bmux and $demux cells.

2022-01-28 23:34:41 +01:00