Marcelina Kościelnicka e64456f920 extract_reduce: Refactor and fix input signal construction. ...

Fixes #3047.

2021-10-21 04:10:01 +02:00

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aiger

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arch

FfData: some refactoring.

2021-10-07 04:24:06 +02:00

asicworld

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bind

Add support for parsing the SystemVerilog 'bind' construct

2021-07-16 09:31:39 -04:00

blif

tests/blif: Add missing gitignore

2021-05-20 12:49:51 +02:00

bram

tests/bram: Do not generate write address collisions.

2021-03-08 16:53:03 +01:00

errors

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fsm

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hana

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liberty

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lut

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memfile

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memories

Fix a regression from #3035.

2021-10-08 15:44:07 +02:00

opt

extract_reduce: Refactor and fix input signal construction.

2021-10-21 04:10:01 +02:00

opt_share

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proc

proc_prune: Make assign removal and promotion per-bit, remember promoted bits.

2021-08-14 15:26:11 +02:00

realmath

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rpc

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sat

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select

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share

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simple

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

simple_abc9

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

smv

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sva

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svinterfaces

Add a test for interfaces on modules loaded on-demand

2021-07-14 22:54:50 -04:00

svtypes

sv: improve support for wire and var with user-defined types

2021-08-12 22:41:41 -06:00

techmap

FfData: some refactoring.

2021-10-07 04:24:06 +02:00

tools

Fixes in vcdcd.pl for newer Perl versions

2021-10-19 10:56:43 +02:00

unit

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various

More deadname stuff

2021-06-09 12:40:33 +02:00

verilog

sv: support wand and wor of data types

2021-09-21 14:52:28 -04:00

vloghtb

Use HTTPS for website links, gatecat email

2021-06-09 12:16:56 +02:00

gen-tests-makefile.sh

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