Clifford Wolf ee65dea738 Fixed signdness detection of expressions with bit- and part-selects

2014-07-28 10:10:08 +02:00

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ast

Fixed signdness detection of expressions with bit- and part-selects

2014-07-28 10:10:08 +02:00

ilang

Fixed ilang parser for new RTLIL API

2014-07-27 11:56:35 +02:00

liberty

Refactoring: Renamed RTLIL::Design::modules to modules_

2014-07-27 11:18:30 +02:00

verific

Fixed verific bindings for new RTLIL api

2014-07-27 12:00:28 +02:00

verilog

Added "make PRETTY=1"

2014-07-24 17:15:01 +02:00

vhdl2verilog

Added passing of various options to vhdl2verilog

2014-07-12 10:02:39 +02:00