KrystalDelusion 82888580ac Merge pull request #5152 from garytwong/unique-if ...

verilog: implement SystemVerilog unique/unique0/priority if semantics.

2025-06-13 09:56:53 +12:00

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_static

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appendix

docs: several small documentation fixes.

2025-05-29 21:26:28 -06:00

cell

docs: mention related effects for multiplexers in the cell library.

2025-05-30 21:43:33 -06:00

code_examples

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getting_started

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using_yosys

abc.rst: Clarify larger-but-slower

2025-05-31 09:10:27 +12:00

yosys_internals

Merge pull request #5152 from garytwong/unique-if

2025-06-13 09:56:53 +12:00

bib.rst

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cell_index.rst

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cmd_ref.rst

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conf.py

Release version 0.54

2025-06-09 07:23:54 +02:00

index.rst

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introduction.rst

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literature.bib

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requirements.txt

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