github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-25 11:56:22 +00:00
Code Issues Releases Wiki Activity
Files
ef5b2777c3a6e3abaa0aa24012bd47e2a2c8a4db
YosysHQ.yosys/frontends
History
whitequark 015b476e56 rtlil: remove dotted identifiers. 
No one knows where they came from and they never did anything useful.
2020-11-25 16:47:20 +00:00
..
aiger
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
ast
Merge pull request #2378 from udif/pr_dollar_high_low
2020-10-01 18:17:36 +02:00
blif
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
json
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
liberty
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
rpc
Fix argument handling in connect_rpc
2020-10-19 13:40:57 +02:00
rtlil
rtlil: remove dotted identifiers.
2020-11-25 16:47:20 +00:00
verific
Update verific version
2020-10-30 08:32:59 +01:00
verilog
Ignore empty parameters in Verilog module instantiations
2020-10-01 18:27:16 +02:00