YosysHQ.yosys/backends/edif at ef7594ce3d3b0fbf08941fb8d4010e73652afd97 - YosysHQ.yosys - Berget Git Service

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Clifford Wolf 0ac72e759d Add generation of logic cells to EDIF back-end runtest.py

2017-03-19 14:57:40 +01:00

..

edif.cc

Fix EDIF: portRef member 0 is always the MSB bit

2017-03-19 14:53:28 +01:00

Makefile.inc

Added edif backend (still under construction)

2013-08-22 11:34:55 +02:00

runtest.py

Add generation of logic cells to EDIF back-end runtest.py

2017-03-19 14:57:40 +01:00