Gary Wong e17ed5df88 verilog: add support for SystemVerilog string literals. ...

Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.

2025-07-10 23:28:22 +02:00

..

extending_yosys

Reinstate #4768

2025-04-08 11:58:05 +12:00

flow

docs: fix verilog frontend internals

2025-07-10 21:15:50 +02:00

formats

Docs: Move rtlil_text (back) to appendix

2024-10-15 07:34:52 +13:00

hashing.rst

hashlib: document merged hash_top_ops with hash_ops

2025-01-20 16:25:52 +01:00

index.rst

Docs: Formatting and fixes

2024-12-18 14:58:51 +01:00

techmap.rst

Docs: Reflow line length

2024-10-15 07:23:45 +13:00

verilog.rst

verilog: add support for SystemVerilog string literals.

2025-07-10 23:28:22 +02:00